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Real time clock module I2 C-BUS INTERFACE REAL TIME CLOCK MODULE Product number (please refer to page 2) RX-8025SA/NB Q41 8 0 2 5 5 x x x x x 0 0 Q41 8 0 2 5 9 x x x x x 0 0 Built-in frequency adjusted 32.768 kHz crystal unit. Compliant with I2C high-speed bus specifications. (400 kHz) Dual Alarm and Timer IRQ function are Available. 32.768 kHz clock frequency output. (FOE, FOUT) Low backup current : 0.48 A/3 V (Typ.) Wide operating voltage range : 1.7 V to 5.5 V Wide timekeeper voltage range : 1.15 V to 5.5 V RX-8025SA RX-8025NB * * * * * * * Actual size The details are mentioned in the application manual. http://www.epsondevice.com The I2C-Bus is a trademark of Philips Electronics N.V. Specifications (characteristics) Absolute Max. rating Item Supply voltage Input voltage Output voltage Storage temperature Range Symbol VDD VI VO1 VO2 TSTG Condition VDD to GND SDA, INT, INTB pins FOUT pin Stored as bare product after unpacking Min. -0.3 GND-0.3 GND-0.5 -55 Max. +6.5 +6.5 +6.5 VDD+0.3 +125 GND=0V Unit Terminal connection RX-8025SA #14 #8 No. 1 2 3 4 5 6 7 Pin terminal N.C SCL FOUT N.C TEST VDD FOE No. 14 13 12 11 10 9 8 Pin terminal N.C SDA INTB GND INTA N.C N.C SCL,SDA,FOE pins GND-0.3 V C #1 #7 Operating range Item Power voltage Clock voltage Operating temperature Symbol VDD VCLK TOPR Condition -- -- No condensation Min. 1.7 1.15 -40 Max. 5.5 +85 GND=0V Unit V C RX-8025NB #22 #14 Frequency characteristics Item Frequency tolerance Oscillation start-up time Frequency temperature characteristics Frequency voltage characteristics Aging Symbol f/f tSTA Top f/V fa Condition Ta=+25 C, VDD=3.0 V Ta=+25 C, VDD=3.0 V Ta=-10C to +70C, VDD=3.0 V ; Reference at +25C Ta=+25 C, VDD=2.0 V to 5.5 V Ta=+25 C, VDD=3.0 V, first year Range AA : 5 5 1 3 Max. +10 -120 1 Max. 5 Max. GND=0V Unit x 10-6 s x 10-6 x 10 -6 #1 #11 No. Pin terminal 1 FOE 2 VDD 3 N.C 4 TEST 5 FOUT 6 SCL 7 SDA 8 INTB 9 GND 10 INTA 11 N.C No. Pin terminal 22 N.C 21 N.C 20 N.C 19 N.C 18 N.C 17 N.C 16 N.C 15 N.C 14 N.C 13 -- 12 -- x 10-6/year External dimensions RX-8025SA (SOP 14-pin) R8025 B E 1234 A 10.10.2 3.1 3.20.1 7.40.2 5.0 (Unit: mm) 1 Equivalent to 15 seconds of monthly deviation (excluding offset.) DC characteristics Item Standby current "H" input voltage "L" input voltage "H" output current "L" output current Symbol IDD2 VIH VIL IOH IOL1 IOL2 IOL3 Input leakage current IIL (GND=0 V, VDD = 1.8 V to 5.5 V, Ta = -40 C to +85 C) Condition Min. Typ. Max. Unit fSCL=0 Hz, FOE = GND INTA, INTB = VDD FOUT ; output off ("L" level) VDD = 3 V 0.8 VDD GND -0.3 0.5 1.0 4.0 -1 0.48 1.20 5.5 0.2 VDD -0.5 A V SCL, SDA, FOE pins FOUT pins, VOH = VDD-0.5 V FOUT pins, VOL = 0.4 V INTA, INTB pins, VOL = 0.4 V SDA pin, VOL = 0.4 V SCL pins, VI = 5.5 V or GND VDD = 5.5 V 0 to 10 0.05 Min. 0.15 1.27 0.35 0.6 mA RX-8025NB (SON 22-pin) 6.3 Max. 4.8 5.00.2 1.3 0.1 1 A R8025 E 1234A 0.5 0.2 85 Real time clock module Register table Address 0 1 2 3 4 5 6 7 8 9 A B C D E F Register symbol Seconds Minutes Hours Weekdays Days Months Years Digital Offset Alarm_W ; Minutes Alarm_W ; Hour Alarm_W ; Weekday Alarm_D ; Minutes Alarm_D ; Hour Reserved Control 1 Control 2 WALE VDSL DALE VDET 12, 24 XST * PON 1 bit 7 o o o o o o Y80 o o o o o o bit 6 S40 M40 o o o o Y40 F6 WM40 o WW6 DM40 o bit 5 S20 M20 H20 P, A o D20 o Y20 F5 WM20 WH20 WP, A WW5 DM20 DH20 DP, A bit 4 S10 M10 H10 o D10 MO10 Y10 F4 WM10 WH10 WW4 DM10 DH10 Reserved TEST * CT2 CTFG CT1 WAFG CT0 DAFG bit 3 S8 M8 H8 o D8 MO8 Y8 F3 WM8 WH8 WW3 DM8 DH8 bit 2 S4 M4 H4 W4 D4 MO4 Y4 F2 WM4 WH4 WW2 DM4 DH4 bit 1 S2 M2 H2 W2 D2 MO2 Y2 F1 WM2 WH2 WW1 DM2 DH2 bit 0 S1 M1 H1 W1 D1 MO1 Y1 F0 WM1 WH1 WW0 DM1 DH1 0 : Always set this bit to "0". AC characteristics Item SCL clock frequency Tolerance spike time on bus Start condition set-up time Start condition Hold time SCL "L" time SCL "H" time SCL and SDA rise time SCL and SDA fall time Data set-up time Data hold time Stop condition set-up time Bus free time Symbol fSCL tSP tSU;STA tHD;STA tLOW tHIGH tr tf tSU;DAT tHD;DAT tSU;STO tBUF Min. - 0.6 1.3 0.6 - 200 0 0.6 1.3 0.3 ns s s Typ. Max. 400 50 Unit kHz ns Block diagram FOUT FOE 32 kHz Output Control Comparator_W Alarm_W Register (Min, Hour, Week) Alarm_D Register (Min, Hour) Voltage Detect VDD Comparator_D Divider Correc -tion OSC Div. Time Counter (Sec, Min, Hour, Week, Day, Month,Year) OSC Detect Address Decoder Address Register I/O Control SCL SDA GND INTA Interrupt Control Shift Register INTB Timing chart Start Condition (s) tSU;STA tLOW Bit 7 MSB (A7) tHIGH Bit6 (A6) 1/fSCL Bit0 LSB (R/W) ACK (A) Stop Condition (P) Start Condition (s) tSU;STA Protocol SCL (S) tr tf (A) tHD;STA tSU;DAT tHD;DAT tSP tSU;STO tHD;STA (P) tBUF (S) SDA 86 |
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